The present invention relates generally to digital data processing devices and, more specifically, to memory controllers in such devices.
Performance demands on digital data processing devices continue to increase at a meteoric pace. For example, in the color printing industry, users demand greater print resolution and color quality. To meet this demand, processors have been developed which operate at higher and higher clock speeds. The instruction sets used to control processors have been pared down (e.g., RISC architecture) to make them more efficient. Processor improvements alone, however, have been insufficient to provide the greater performance required by users. The other subsystems which support the processor, e.g., I/O devices and memory devices, must also be designed to operate at higher speeds and support greater bandwidth. For example, one RISC performance goal is to achieve memory throughput of one data word per clock cycle.
Dynamic random access memory (DRAM) is one of the different types of memory subsystems which are commonly shared in such systems. Recently, DRAM has been provided in the form of memory chips each of which can be inserted into standardized sockets on a printed circuit board. Each memory chip typically includes a matrix array of memory locations each of which can store one or more bits. For example, a 16 megabit DRAM chip could be fabricated as a device having either 16M one-bit locations or a device having 4M four-bit locations. As DRAM fabrication technology has improved, the number of individual memory locations available in each memory chip has rapidly increased. The memory capacity of DRAM chips which are currently in use range from, for example, 256 kilobits to 16 megabits, with larger capacities expected in the future. Note that throughout this specification the abbreviation MB refers to "megabyte" or "megabytes" rather than megabit or megabits.
Each memory location within a DRAM chip has a unique address. In order to perform a memory operation involving a DRAM array, an address identifying the particular location involved in the operation must be sent to the correct DRAM chip(s). Once an incoming address is received by a memory controller, it is first decoded to identify the particular DRAM bank in which the DRAM chip of interest is grouped for addressing purposes. A row address derived from the incoming system address is placed on the DRAM address bus and strobed into the identified DRAM bank in response to a row address strobe (RAS) signal sent from the memory controller selecting the identified DRAM bank. Next, a column address is placed on the DRAM address bus connecting the memory controller and the DRAM and the column address is strobed into the selected DRAM bank by the column address strobe (CAS). These row and column addresses are multiplexed onto a set of address signal lines to reduce the number of lines necessary to address the DRAMs.
As mentioned above, a significant consideration in controlling DRAM is the speed at which data can be retrieved from (or written to)memory. One technique which is commonly used to increase access speed to and from the DRAM is called interleaving. Interleaved memory banks each alternatingly contain adjacent data words which can be accessed in parallel. For example, if a first bank in an interleaved pair contains a data word having a word address of 00001, a second bank in the interleaved pair will contain the adjacent data word having a word address of 00010. Thus, a system request to read these words can be performed by a memory controller more rapidly than if these words were stored sequentially in the same DRAM chip of one DRAM bank.
In addition to access speed, another desirable characteristic in memory subsystems is the provision of a flexible upgrade path. Ideally, a memory controller will be designed to allow end users to add new DRAM chips to the memory subsystems interchangeably with the DRAM chips available at the time that the memory controller was designed. Naturally, from a consumer point of view, flexibility in the upgrade path is a significant factor in considering product life cycle values, since end users will be concerned that new generations of DRAM chips might render the memory controller obsolete. As part of the strategy which allows designers to predict the requirements for controlling new generations of DRAM chips, many standards have been implemented in this area. For example, in the area of DRAM chip design, one standard which has been adopted is the use of row followed by column address multiplexing circuitry between a system bus and the DRAM arrays. Timing of the various address and control signals sent from the memory controller to the DRAM has also been standardized to within predetermined tolerances. To date, however, no known DRAM controllers exist which provide industry standard compatibility and which provide a technique for populating DRAM banks as desired interchangeably and then operating the DRAM in either an interleaved or non-interleaved manner based upon the types the DRAM chips chosen to populate the DRAM banks.